Bus Encoding Technique for hierarchical memory system

In microprocessor-based systems, data and address buses are the core of the interface between a microprocessor and the external world. The increasing gap between interfaces has pushed CPU designers to increase the bandwidth of the data transfer. Moreover, modern software applications span a very large address space. With very wide address and data busses, the power dissipation on bus interfaces is becoming a major concern. In microprocessor-based systems, large power savings can be achieved through reduction of the transition activity of the onand off-chip busses. This is because the total capacitance being switched when a voltage change occurs on a bus line is usually larger than the capacitive load that must be charged/discharged when internal nodes toggle. Encoding techniques are very effective in limiting the number of signal transitions on the bus lines. The microprocessor-based systems are incorporated with hierarchical memory systems. The characteristics of addresses on the bus in hierarchical memory can be very random. So our goal is to study the performance of existing bus encoding techniques (T0 code [1] and Bus-invert code [2]) for different types of memory hierarchies (e.g. main memory, L1, and L2 caches).